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single-/dual-supply, high voltage isolated igbt gate driver data sheet adum4136 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features 4 a peak drive output capability output power device resistance: <1 desaturation protection isolated fault output soft shutdown on fault isolated fault and ready functions low propagation delay: 55 ns typical minimum pulse width: 50 ns operating temperature range: ?40c to +125c output voltage range to 35 v input voltage range from 2.5 v to 6 v output and input undervoltage lockout (uvlo) creepage distance: 7.8 mm minimum 100 kv/s minimum common-mode transient immunity (cmti) 20-year lifetime for 600 v rms or 1092 v dc working voltage safety and regulatory approvals (pending) 5 kv ac for 1 minute per ul 1577 csa component acceptance notice 5a din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 849 v peak (basic) applications mosfet/igbt gate drivers photovoltaic (pv) inverters motor drives power supplies general description the adum4136 is a single-channel gate driver specifically optimized for driving insulated gate bipolar transistors (igbts). analog devices, inc., i coupler? technology provides isolation between the input signal and the output gate drive. operation with unipolar or bipolar secondary supplies is possible, allowing negative gate drive if needed. the analog devices chip scale transformers also provide isolated communication of control information between the high voltage and low voltage domains of the chip. information on the status of the chip can be read back from dedicated outputs. control of resetting the device after a fault on the secondary side is performed on the primary side of the device. integrated onto the adum4136 is a desaturation detection circuit that provides protection against high voltage short- circuit igbt operation. the desaturation protection contains noise reducing features such as a 312 ns (typical) masking time after a switching event to mask voltage spikes due to initial turn-on. an internal 537 a (typical) current source allows low device count, and the internal blanking switch allows the addition of an external current source if more noise immunity is needed. the secondary uvlo is set to 12 v with common igbt threshold levels taken into consideration. functional block diagram master logic primary gnd 2 v i + v i ? ready 1 2 7 16 v ss2 15 v ss1 4 v ss1 8 fault 6 v dd1 3 master logic secondary uvlo uvlo tsd encode decode decode encode v out 11 v ss2 9 v ss2 10 v dd2 13 v dd2 12 reset 5 9v desat 14 adum4136 notes 1. grounds on primary and secondary side are isolated from each other. 13575-001 1 1 1 1 1 2 2 2 2 2 2 figure 1.
adum4136* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? adum4136 evaluation board documentation application notes ? an-1316: generating multiple isolated bias rails for igbt motor drives with flyback, sepic, and ?uk combination data sheet ? adum4136: single-/dual-supply, high voltage isolated igbt gate driver data sheet user guides ? ug-1019: evaluation board for the adum4136 i coupler, dual-supply, high voltage, isolated igbt gate driver tools and simulations ? adum4136 ibis model reference materials technical articles ? gate drive and current feedback signal isolation in industrial motor drives design resources ? adum4136 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all adum4136 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
adum4136 data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics ............................................................. 3 ? package characteristics ............................................................... 4 ? regulatory information ............................................................... 4 ? insulation and safety related specifications ............................ 4 ? din v vde v 0884-10 (vde v 0884-10) insulation characteristics .............................................................................. 5 ? recommended operating conditions ...................................... 5 ? absolute maximum ratings ............................................................ 6 ? esd caution...................................................................................6 ? pin configuration and function descriptions ..............................7 ? typical performanace characteristics ............................................8 ? applications information .............................................................. 11 ? pcb layout ................................................................................. 11 ? propagation delay related parameters ................................... 11 ? protection features .................................................................... 11 ? power dissipation....................................................................... 13 ? dc correctness and magnetic field immunity ........................... 13 ? insulation lifetime ..................................................................... 13 ? typical application .................................................................... 15 ? outline dimensions ....................................................................... 16 ? ordering guide .......................................................................... 16 ? revision history 7/2016revision 0: initial version
data sheet adum4136 rev. 0 | page 3 of 16 specifications electrical characteristics low-side voltages are referenced to v ss1 . high-side voltages are referenced to gnd 2 ; 2.5 v v dd1 6 v, 12 v v dd2 35 v, and t j = ?40c to +125c. all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. all typic al specifications are at t j = 25c, v dd1 = 5.0 v, v ss2 = 0 v, and v dd2 = 15 v. table 1. parameter symbol min typ max unit test conditions/comments dc specifications high-side power supply input voltage v dd2 v dd2 12 35 v v dd2 ? v ss2 35 v v ss2 v ss2 ?15 0 v input current, quiescent ready high v dd2 i dd2 (q) 3.62 4.49 ma v ss2 i ss2 (q) 4.82 6.21 ma logic supply v dd1 input voltage v dd1 2.5 6 v input current i dd1 output low 1.78 2.17 ma output signal low output high 4.78 5.89 ma output signal high logic inputs (v i +, v i ?, reset ) input current (v i +, v i ? only) i i ?1 +0.01 +1 a input voltage logic high v ih 0.7 v dd1 v 2.5 v v dd1 ? v ss1 5 v 3.5 v v dd1 ? v ss1 > 5 v logic low v il 0.3 v dd1 v 2.5 v v dd1 ? v ss1 5 v 1.5 v v dd1 ? v ss1 > 5 v reset internal pull-down r reset _pd 300 k undervoltage lockout (uvlo) v dd1 positive going threshold v vdd1uv+ 2.43 2.49 v negative going threshold v vdd1uv? 2.29 2.34 v hysteresis v vdd1uvh 0.09 v v dd2 positive going threshold v vdd2uv+ 11.6 12.0 v negative going threshold v vdd2uv? 10.4 11.2 v hysteresis v vdd2uvh 0.4 v fault pull-down fet resistance r fault _pd_fet 11 50 tested at 5 ma ready pull-down fet resistance r rdy_pd_fet 11 50 tested at 5 ma desaturation (desat) desaturation detect comparator voltage v desat, th 8.66 9.2 9.57 v internal current source i desat_src 466 537 592 a thermal shutdown (tsd) tsd positive edge t tsd_pos 155 c tsd hysteresis t tsd_hyst 20 c internal nmos gate on resistance r dson_n 322 625 m tested at 250 ma 325 625 m tested at 1 a internal pmos gate on resistance r dson_p 475 975 m tested at 250 ma 480 975 m tested at 1 a soft shutdown nmos on resistance r dson_fault 10.4 22 tested at 250 ma peak current 4.61 a v dd2 = 12 v, 2 gate resistance switching specifications pulse width 1 pw 50 ns c l = 2 nf, v dd2 = 15 v, r gon 2 = r goff 2 = 3.9 reset debounce t deb_ reset 500 615 700 ns
adum4136 data sheet rev. 0 | page 4 of 16 parameter symbol min typ max unit test conditions/comments propagation delay 3 t dhl , t dlh 40 55 68 ns c l = 2 nf, v dd2 = 15 v, r gon 2 = r goff 2 = 3.9 propagation delay skew 4 t psk 15 ns c l = 2 nf, r gon 2 = r goff 2 = 3.9 output rise/fall time (10% to 90%) t r /t f 11 16 22.9 ns c l = 2 nf, v dd2 = 15 v, r gon 2 = r goff 2 = 3.9 blanking capacitor discharge switch masking t desat_delay 213 312 615 ns time to report desaturation fault to fault pin t report 1.3 2 s common-mode transient immunity (cmti) |cm| static cmti 5 100 kv/s v cm = 1500 v dynamic cmti 6 100 kv/s v cm = 1500 v 1 the minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 2 see the power dissipation section. 3 t dlh propagation delay is measured from the time of the input rising logic high threshold, v ih , to the output rising 10% threshold of the v out signal. t dhl propagation delay is measured from the input falling logic low threshold, v il , to the output falling 90% threshold of the v out signal. see figure 22 for waveforms of propagation delay parameters. 4 t psk is the magnitude of the worst case difference in t dlh and/or t dhl that is measured between units at the same operating temperature , supply voltages, and output load within the recommended operating conditions. see figure 22 for waveforms of propagation delay parameters. 5 static common-mode transie nt immunity is defined as the largest dv/dt between v ss1 and v ss2 with inputs held either high or lo w such that the output voltage remains either above 0.8 v dd2 for output high, or 0.8 v for output low. operation with transients above the recommended levels can cause momentary data upse ts. 6 dynamic common-mode transie nt immunity is defined as the largest dv/dt between v ss1 and v ss2 with the switching edge coincident with the transient test pulse. operation with transients above the recommended levels can cause momentary data upsets. package characteristics table 2. parameter symbol min typ max unit test conditions/comments resistance (input side to high-side output) 1 r i-o 10 12 capacitance (input side to high-side output) 1 c i-o 2.0 pf input capacitance c i 4.0 pf junction to ambient thermal resistance ja 75.4 c/w 4-layer printed circuit board (pcb) junction to case thermal resistance jc 35.4 c/w 4-layer pcb 1 the device is considered a two-terminal device: pin 1 through pin 8 are shorted together, and pin 9 through pin 16 are shorted together. regulatory information the adum4136 is pending approval by the organizations listed in table 3. table 3. ul (pending) csa (pending) vde (pending) recognized under ul 1577 component recognition program 1 approved under csa component acceptance no tice 5a certified according to vde0884-10 2 single protection, 5000 v rms isolation voltage basic insulation per csa 60950-1-07+a1+a2 and iec 60950-1 2 nd ed.+a1+a2, 780 v rms (1103 v peak) maximum working voltage basic insulation, 849 v peak csa 60950-1-07+a1+a2 and iec 60950-1 second ed.+a1+a2, 390 v rms (551 v peak) maximum working voltage file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, each adum4136 is proof tested by applying an insulation test voltage 6000 v rms for 1 second (current le akage detection limit = 10 a). 2 in accordance with di n v vde v 0884-10, each adum4136 is proof tested by applying an insulation test voltage 1590 v peak for 1 se cond (partial discharge detection limit = 5 pc). an asterisk (*) marking brande d on the component designates din v vde v 0884-10 approval. insulation and safety related specifications table 4. parameter symbol value unit test conditions/comments rated dielectric insulation voltage 5000 v rms 1-minute duration minimum external air gap (clearance) l(i01) 7.8 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 7.8 min mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.026 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >400 v din iec 112/vde 0303 part 1 isolation group ii material gr oup (din vde 0110, 1/89, table 1)
data sheet adum4136 rev. 0 | page 5 of 16 din v vde v 0884-10 (vde v 0884-10) insulation characteristics maintenance of the safety data is ensured by protective circuits. the asterisk (*) marking on the package denotes din v vde v 0 884-10 approval for a 560 v peak working voltage. table 5. vde characteristics description test conditions/comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classificat ion 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 849 v peak input to output test voltage, method b1 v iorm 1.875 = v pd (m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd (m) 1592 v peak input to output test voltage, method a after environmental tests subgroup 1 v iorm 1.5 = v pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd (m) 1274 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd (m) 1019 v peak highest allowable overvoltage v iotm 8000 v peak surge isolation voltage v peak = 12.8 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 8000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 2) maximum junction temperature t s 150 c safety total dissipated power p s 2.77 w insulation resistance at t s v io = 500 v r s >10 9 safe operating power (w) ambient temperature (c) 05 0 3.0 2.5 2.0 1.5 1.0 0.5 0 100 150 200 13575-002 figure 2. thermal derating curve, dependence of safety limiting values on case temperature, per din v vde v 0884-10 recommended operat ing conditions table 6. parameter value operating temperature range (t a ) ?40c to +125c supply voltages v dd1 1 2.5 v to 6 v v dd2 2 12 v to 35 v v dd2 ? v ss2 2 12 v to 35 v v ss2 2 ?15 v to 0 v input signal rise/fall time 1 ms static common mode transient immunity 3 ?100 kv/s to +100 kv/s dynamic common mode transient immunity 4 ?100 kv/s to +100 kv/s 1 referenced to v ss1 . 2 referenced to gnd 2 . 3 static common-mode transient immunity is defined as the largest dv/dt between v ss1 and v ss2 with inputs held either high or low such that the output voltage remains either above 0.8 v dd2 for output high, or 0.8 v for output low. operation with transients above recommended levels can cause momentary data upsets. 4 dynamic common-mode transient immunity is defined as the largest dv/dt between v ss1 and v ss2 with the switching edge coincident with the transient test pulse. operation with transients above recommended levels can cause momentary data upsets.
adum4136 data sheet rev. 0 | page 6 of 16 absolute maximum ratings table 7. parameter rating storage temperature range (t st ) ?55c to +150c junction operating temperature range (t j ) ?40c to +125c supply voltage v dd1 to v ss1 ?0.3 v to +6.5 v v dd2 to gnd 2 ?0.3 v to +40 v v ss2 to gnd 2 ?20 v to +0.3 v v dd2 ? v ss2 40 v input voltage v desat 1 ?0.3 v to v dd2 + 0.3 v v i +, 2 v i ?, 2 reset 2 ?0.3 v to +6.5 v output voltage v out 3 ?0.3 v to v dd2 + 0.3 v common-mode transients (|cm|) ?150 kv/s to +150 kv/s 1 referenced to gnd 2 . 2 referenced to v ss1 . 3 referenced to v ss2 . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. table 8. maximum continuous working voltage 1 parameter value constraint 60 hz ac voltage 600 v rms 20-year lifetime at 0.1% failure rate, zero average voltage dc voltage 1092 v peak limited by the creepage of the package, pollution degree 2, material group ii 2, 3 1 see the insulation lifetime section for details. 2 other pollution degree and material grou p requirements yield a different limit. 3 some system level standards allow components to use the printed wiring board (pwb) creepage values. the supported dc voltage may be higher for those standards. esd caution table 9. truth table (positive logic) 1 v i + input v i ? input reset pin ready pin fault pin v dd1 state v dd2 state v gate 2 l l h h h powered powered l l h h h h powered powered l h l h h h powered powered h h h h h h powered powered l x x h l unknown powered powered l x x h unknown l powered powered l l l h l unknown unpowered powered l x x l 3 unknown h 3 powered powered l x x x l unknown powered unpowered unknown 1 l is low, h is high, and x is dont care. 2 v gate is the voltage of the gate being driven. 3 time dependent value. see figure 22 for details on timing.
data sheet adum4136 rev. 0 | page 7 of 16 pin configuration and fu nction descriptions v i + 1 v i ? 2 v dd1 3 v ss1 4 gnd 2 16 v ss2 15 desat 14 v dd2 13 reset 5 v dd2 12 fault 6 v out 11 ready 7 v ss2 10 v ss1 8 v ss2 9 adum4136 top view (not to scale) 13575-003 figure 3. pin configuration table 10. pin function descriptions pin no. mnemonic description 1 v i + positive logic cmos input drive signal. 2 v i ? negative logic cmos input drive signal. 3 v dd1 input supply voltage on primary side, 2.5 v to 6 v. the supply that is connected to this pin must be referenced to v ss1 . 4 v ss1 ground reference for primary side. 5 reset cmos input. when a fault exists, bring this pin low to clear the fault. reset has an internal 300 k pull-down resistor. 6 fault open-drain logic output. connect this pin to a pull-up resistor to read the signal. a low state on this pin indicates when a desaturation fault has occurred. the presence of a fault condition precludes the gate drive output from going high. 7 ready open-drain logic output. connect this pin to a pull-up resistor to read the signal. a high state on this pin indicates that the device is functional and ready to operate as a gate driver. if ready is low, the gate drive output is precluded from going high. 8 v ss1 ground reference for primary side. 9 v ss2 negative supply for secondary side, ?15 v to 0 v. the supply that is connected to this pin must be referenced to gnd 2 . 10 v ss2 negative supply for secondary side, ?15 v to 0 v. the supply that is connected to this pin must be referenced to gnd 2 . 11 v out gate drive output current path for the device. 12 v dd2 secondary side input supply voltage, 12 v to 35 v. the supp ly that is connected to this pin must be referenced to gnd 2 . 13 v dd2 secondary side input supply voltage, 12 v to 35 v. the supp ly that is connected to this pin must be referenced to gnd 2 . 14 desat detection of desaturation condition. connect this pin to an external current source or a pull-up resistor. a fault on this pin asserts a fault on the fault pin on the primary side. until the fault is cleared on the primary side, the gate drive is suspended. during a fault condition, a smaller turn-off fet slowly brings the gate voltage down. 15 v ss2 negative supply for secondary side, ?15 v to 0 v. the supply that is connected to this pin must be referenced to gnd 2 . 16 gnd 2 ground reference for secondary side. connect this pin to the emitter of the igbt or the source of the mosfet being driven.
adum4136 data sheet rev. 0 | page 8 of 16 typical performanace characteristics ch1 2v ch2 5v 100ns/div ch1 = v i + (2v/div) ch2 = v gate (5v/div) 10gs/s 100ps/pt a ch1 1.68v 1 2 13575-004 figure 4. input to output waveform, 2 nf load, 5.1 series gate resistor, v dd1 = +5 v, v dd2 = +15 v, v ss2 = ?5 v ch1 2v ch2 5v 100ns/div ch1 = v i + (2v/div) ch2 = v gate (5v/div) 10gs/s 100ps/pt a ch1 1.68v 1 2 13575-005 figure 5. input to output waveform, 2 nf load, 5.1 series gate resistor, v dd1 = 5 v, v dd2 = 15 v, v ss2 = 0 v ch1 2v ch2 5v 100ns/div ch1 = v i + (2v/div) ch2 = v gate (5v/div) 10gs/s 100ps/pt a ch1 1.68v 1 2 13575-006 figure 6. input to output waveform, 2 nf load, 4.0 series gate resistor, v dd1 = +5 v, v dd2 = +15 v, v ss2 = ?5 v ch1 2v ch2 5v 100ns/div ch1 = v i + (2v/div) ch2 = v gate (5v/div) 10gs/s 100ps/pt a ch1 1.68v 1 2 13575-007 figure 7. input to output waveform, 2 nf load, 4.0 series gate resistor, v dd1 = 5 v, v dd2 = 15 v, v ss2 = 0 v ch1 2v ch2 5v 100ns/div ch1 = v i + (2v/div) ch2 = v gate (5v/div) 10gs/s 100ps/pt a ch1 1.68v 1 2 13575-008 figure 8. input to output waveform, 2 nf load, 2.0 series gate resistor, v dd1 = +5 v, v dd2 = +15 v, v ss2 = ?5 v ch1 2v ch2 5v 100ns/div ch1 = v i + (2v/div) ch2 = v gate (5v/div) 10gs/s 100ps/pt a ch1 1.68v 1 2 13575-009 figure 9. input to output waveform, 2 nf load, 2.0 series gate resistor, v dd1 = 5 v, v dd2 = 15 v, v ss2 = 0 v
data sheet adum4136 rev. 0 | page 9 of 16 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 100 200 300 400 500 600 700 800 900 1000 i dd1 (ma) frequency (khz) v dd1 = 2.5v v dd1 = 3.3v v dd1 = 5.0v 13575-010 figure 10. i dd1 current vs. frequency, duty = 50%, v i + = v dd1 60 0 10 20 30 40 50 0 100 200 300 400 500 600 700 800 900 1000 i dd2 (ma) frequency (khz) v dd2 = 12v v dd2 = 15v v dd2 = 20v 13575-011 figure 11. i dd2 current vs. frequency, duty = 50%, 2 nf load, v ss2 = 0 v ch1 5v ch3 10v ch2 5v 10s/div ch1 = v i + (5v/div) ch2 = v gate (5v/div) ch3 = v dd2 (10v/div) 100ms/s 100ns/pt a ch3 8.8v 1 2 3 13575-012 figure 12. typical v dd2 startup to output valid 80 70 60 0 10 20 30 40 50 12 14 16 18 20 22 24 26 28 30 propagation delay (ns) v dd2 (v) t dhl t dlh 13575-013 figure 13. propagation delay vs. output supply voltage (v dd2 ), v dd1 = 5 v 30 0 5 10 15 20 25 12 14 16 18 20 22 24 26 28 30 rise/fall time (ns) v dd2 (v) t r t f 13575-014 figure 14. rise/fall time vs. v dd2 , v dd2 ? v ss2 = 12 v, v dd1 = 5 v, 2 nf load, r g = 5.1 80 70 60 0 10 20 30 40 50 2.5 2.8 3.3 3.8 4.3 4.8 5.3 5.8 propagation delay (ns) input supply voltage (v) t dhl t dlh 13575-015 figure 15. propagation delay vs. input supply voltage, v dd2 ? v ss2 = 12 v
adum4136 data sheet rev. 0 | page 10 of 16 80 70 60 0 10 20 30 40 50 ?40 ?20 0 20 40 60 80 100 120 propagation delay (ns) ambient temperature (c) t dhl t dlh 13575-016 figure 16. propagation delay vs. ambient temperature, v dd2 = 5 v, v dd2 ? v ss2 = 12 v ch1 5v ch3 5v ch2 10v ch4 5v 500ns/div ch1 = v i + (5v/div) ch2 = v gate (10v/div) ch3 = fault (5v/div) ch4 = desat (5v/div) 2.5gs/s 400ps/pt a ch1 1.1v 1 2 4 3 13575-017 figure 17. example desaturation event and reporting 800 700 600 0 100 200 300 400 500 ?40 ?20 0 20 40 60 80 100 120 r dson (m ? ) temperature (c) source resistance sink resistance 13575-018 figure 18. output on resistance (r dson ) vs. temperature, v dd2 = 15 v, tested at 250 ma 800 700 600 0 100 200 300 400 500 ?40 ?20 0 20 40 60 80 100 120 r dson (m ? ) temperature (c) source resistance sink resistance 13575-019 figure 19. output on resistance (r dson ) vs. temperature, v dd2 = 15 v, tested at 1 a ch1 5v ch3 5v ch2 5v 500ns/div ch1 = v i + (5v/div) ch2 = v gate (5v/div) 2.5gs/s 400ps/pt a ch3 3.3v 1 2 3 ch3 = reset (5v/div) 13575-020 figure 20. example reset to output valid 10 9 8 7 6 0 1 2 3 4 5 12.0 14.5 17.0 19.5 22.0 24.5 peak output current (a) output supply voltage (v) peak sink i out peak source i out 13575-021 figure 21. peak output current vs. output supply voltage, 2.4 series resistance (i out is the current going into/out of the device gate)
data sheet adum4136 rev. 0 | page 11 of 16 applications information pcb layout the adum4136 igbt gate driver requires no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins. use a small ceramic capacitor with a value between 0.01 f and 0.1 f to provide a good high frequency bypass. on the output power supply pin, v dd2 , it is recommended to add a 10 f capacitor to provide the charge required to drive the gate capacitance at the adum4136 outputs. on the output supply pin, avoid the use of vias on the bypass capacitor or employ multiple vias to reduce the inductance in the bypassing. the total lead length between both ends of the smaller capacitor and the input or output power supply pin must not exceed 5 mm. propagation delay related parameters propagation delay describes the time required for a logic signal to propagate through a component. the propagation delay to a low output can differ from the propagation delay to a high output. the adum4136 specifies t dlh as the time between the rising input high logic threshold (v ih ) to the output rising 10% threshold (see figure 22). likewise, the falling propagation delay (t dhl ) is defined as the time between the input falling logic low threshold (v il ) and the output falling 90% threshold. the rise and fall times are dependent on the loading conditions and are not included in the propagation delay, which is the industry standard for gate drivers. output input 90% 10% v ih v il t dlh t r t f t dhl 13575-022 figure 22. propagation delay parameters propagation delay skew refers to the maximum amount that the propagation delay differs between multiple adum4136 components operating under the same temperature, input voltages, and load conditions. protection features fault reporting the adum4136 provides protection for faults that may occur during the operation of an igbt. the primary fault condition is desaturation. if saturation is detected, the adum4136 shuts down the gate drive and asserts fault low. the output remains disabled until reset is brought low for more than 500 ns and is then brought high. fault is reset to high on the falling edge of reset . while reset remains held low, the output remains disabled. the reset pin has an internal, 300 k pull-down resistor. desaturation detection occasionally, component failures or faults occur with the circuitry connected to the igbt connected to the adum4136 . examples include shorts in the inductor/motor windings or shorts to power/ground buses. the resulting excess in current flow causes the igbt to come out of saturation. to detect this condition and to reduce the likelihood of damage to the fet, a threshold circuit is used on the adum4136 . if the desat pin exceeds the typical desaturation threshold (v desat, th ) of 9.2 v while the high-side driver is on, the adum4136 enters the failure state and turns the igbt off. at this time, the fault pin is brought low. an internal current source of 537 a (typical) is provided, as well as the option to boost the charging current using external current sources or pull-up resistors. the adum4136 has a built-in blanking time to prevent false triggering while the igbt first turns on. the time between desaturation detection and reporting a desaturation fault to the fault pin is less than 2 s (t report ). bring reset low to clear the fault. there is a 500 ns (minimum) debounce (t deb_ reset ) on the reset pin. the time, t desat_delay , shown in figure 23, provides approximately 312 ns (typical) of masking time that keeps the internal switch that grounds the blanking capacitor tied low for the initial portion of the igbt on time. v desat v dd2 v f 9v fault v ce 9v <200ns v gate desat switch on off off v i + desat event on on ~2s recommended t report < 2s t desat_delay = 300ns 13575-023 figure 23. desaturation detection timing diagram
adum4136 data sheet rev. 0 | page 12 of 16 for the following design example, see the schematic shown in figure 29 along with the timing diagrams in figure 23. under normal operation, during igbt off times, the voltage across the igbt (v ce ) rises to the rail voltage supplied to the system. in this case, the blocking diode shuts off, protecting the adum4136 from high voltages. during the off times, the internal desaturation switch is on, accepting the current going through the r blank resistor, which allows the c blank capacitor to remain at a low voltage. for the first 312 ns (typical) of the igbt on time, the internal desaturation switch remains on, clamping the desat pin voltage low. after the 312 ns (typical) delay time, the desat pin is released, and the desat pin is allowed to rise towards v dd2 either by the internal current source on the desat pin, or additionally with an optional external pull-up resistor, r blank , to increase the current drive if it is not clamped by the collector or drain of the switch being driven. r desat is chosen to dampen the current at this time, typically selected around 100 to 2 k. select the blocking diode to block above the high rail voltage on the collector of the igbt and to be a fast recovery diode. in the case of a desaturation event, v ce rises above the 9.2 v threshold in the desaturation detection circuit. if no r blank resistor is used to increase the blanking current, the voltage on the blanking capacitor, c blank , rises at a rate of 537 a (typical) divided by the c blank capacitance. depending on the igbt specifications, a blanking time of approximately 2 s is a typical design choice. when the desat pin rises above the 9.2 v threshold, a fault registers, and within 200 ns, the gate output drives low. the output is brought low using the n-fet fault mosfet, which is approximately 35 times more resistive than the internal gate driver n-fet, to perform a soft shutdown to reduce the chance of an overvoltage spike on the igbt during an abrupt turn-off event. within 2 s, the fault is communicated back to the primary side fault pin. to clear the fault, a reset is required. thermal shutdown if the internal temperature of the adum4136 exceeds 155c (typical), the device enters thermal shutdown (tsd). during the thermal shutdown time, the ready pin is brought low on the primary side, and the gate drive is disabled. when tsd occurs, the device does not leave tsd until the internal temperature drops below 135c (typical), at which time the ready pin returns to high, and the device exits shutdown. undervoltage lockout (uvlo) faults uvlo faults occur when the supply voltages are below the specified uvlo threshold values. during a uvlo event on either the primary side or secondary side, the ready pin goes low, and the gate drive is disabled. when the uvlo condition is removed, the device resumes operation, and the ready pin goes high. ready pin the open-drain ready pin is an output that confirms communi- cation between the primary to secondary sides is active. the ready pin remains high when there are no uvlo or tsd events present. when the ready pin is low, the igbt gate is driven low. table 11. ready pin logic table uvlo tsd ready pin output no no high yes no low no yes low yes yes low fault pin the open-drain fault pin is an output to communicate that a desaturation fault has occurred. when the fault pin is low, the igbt gate is driven low. if a desaturation event occurs, the reset pin must be driven low for at least 500 ns, then high to return operation to the igbt gate drive. reset pin the reset pin has an internal 300 k (typical) pull-down resistor. the reset pin accepts cmos level logic. when the reset pin is held low, after a 500 ns debounce time, any faults on the fault pin are cleared. while the reset pin is held low, the switch on v out is closed, bringing the gate voltage of the igbt low. when reset is brought high, and no fault exists, the device resumes operation. reset fault <500ns 500ns 13575-024 figure 24. reset timing v i + and v i ? operation the adum4136 has two drive inputs, v i + and v i ?, to control the igbt gate drive signal, v out . both the v i + and v i ? inputs use cmos logic level inputs. the input logic of the v i + and v i ? pins can be controlled by either asserting v i + high or v i ? low. with the v i ? pin low, the v i + pin accepts positive logic. if v i + is held high, the v i ? pin accepts negative logic. if a fault is asserted, transmission is blocked until the fault is cleared by the reset pin. v i + fault v i ? v out 13575-025 figure 25. v i + and v i ? block diagram the minimum pulse width is the minimum period in which the timing specifications are guaranteed.
data sheet adum4136 rev. 0 | page 13 of 16 gate resistance selection it is generally desired to have the turn off occur faster than the turn on. to select the series resistance, decide what the maximum allowed peak current is for the igbt. knowing the voltage swing on the gate, as well as the internal resistance of the gate driver, an external resistor can be chosen. i peak = ( v dd2 ? v ss2 )/( r dson_n + r goff ) for example, if the turn-off peak current is 4 a, with a (v dd2 ? v ss2 ) of 18 v, r goff = (( v dd2 ? v ss2 ) ? i peak r dson_n )/ i peak r goff = (18 v ? 4 a 0.6 )/4 a = 3.9 after r goff is selected, a slightly larger r gon can be selected to arrive at a slower turn-on time. power dissipation during the driving of an igbt gate, the driver must dissipate power. this power is not insignificant and can lead to tsd if considerations are not made. the gate of an igbt can be roughly simulated as a capacitive load. due to miller capacitance and other nonlinearities, it is common practice to take the stated input capacitance, c iss , of a given igbt, and multiply it by a factor of 5 to arrive at a conservative estimate to approximate the load being driven. with this value, the estimated total power dissipation in the system due to switching action, p diss , is given by p diss = c est ( v dd2 ? v ss2 ) 2 f s where: c est = c iss 5. f s is the switching frequency of the igbt. this power dissipation is shared between the internal on resistances of the internal gate driver switches and the external gate resistances, r gon and r goff . the ratio of the internal gate resistances to the total series resistance allows the calculation of losses seen within the adum4136 chip. p diss_adum4136 = p diss 0.5(r dson_p /( r gon + r dson_p ) + r dson_n /( r goff + r dson_n )) taking the power dissipation found inside the chip and multiplying it by the ja gives the rise above ambient temperature that the adum4136 experiences. t adum4136 = ja p diss_adum4136 + t amb for the device to remain within specification, t adum4136 must not exceed 125c. if t adum4136 exceeds 155c (typical), the device enters thermal shutdown. dc correctness and magnetic field immunity the adum4136 is resistant to external magnetic fields. the limitation on the adum4136 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which a false reading condition can occur. the 2.5 v operating condition of the adum4136 is examined because it represents the most susceptible mode of operation. 100 10 1 0.1 0.01 0.001 1k 10k 100k 1m 10m 100m maximum allowable magnetic flux density (kgauss) magnetic field frequency (hz) 13575-026 figure 26. maximum allowable external magnetic flux density 1k 100 10 1 0.1 0.01 1k 10k 100k 1m 10m 100m maximum allowable current (ka) magnetic field frequency (hz) distance = 1m distance = 100mm distance = 5mm 13575-027 figure 27. maximum allowable cu rrent for various current to adum4136 spacings insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation, as well as on the materials and material interfaces. two types of insulation degradation are of primary interest: breakdown along surfaces exposed to air and insulation wear out. surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation.
adum4136 data sheet rev. 0 | page 14 of 16 surface tracking surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. lower material group ratings are more resistant to surface tracking and therefore can provide adequate lifetime with smaller creepage. the minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. the material group and creepage for the adum4136 isolator are presented in table 4. insulation wear out the lifetime of insulation caused by wear out is determined by its thickness, material properties, and the voltage stress applied. it is important to verify that the product lifetime is adequate at the application working voltage. the working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. the working voltage applicable to tracking is specified in most standards. testing and modeling show that the primary driver of long- term degradation is displacement current in the polyimide insulation causing incremental damage. the stress on the insulation can be broken down into broad categories, such as dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. the ratings in certification documents are usually based on 60 hz sinusoidal stress because this stress reflects isolation from line voltage. however, many practical applications have combinations of 60 hz ac and dc across the barrier as shown in equation 1. because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as shown in equation 2. for insulation wear out with the polyimide materials used in this product, the ac rms voltage determines the product lifetime. 22 dc rmsac rms vvv ?? (1) or 22 dc rms rmsac vvv ?? (2) where: v rms is the total rms working voltage. v ac rms is the time varying portion of the working voltage. v dc is the dc offset of the working voltage. calculation and use of parameters example the following is an example that frequently arises in power conversion applications. assume that the line voltage on one side of the isolation is 240 v ac rms, and a 400 v dc bus voltage is present on the other side of the isolation barrier. the isolator material is polyimide. to establish the critical voltages in determining the creepage clearance and lifetime of a device, see figure 28 and the following equations. isolation voltag e time v ac rms v rms v dc v peak 13575-028 figure 28. critical voltage example the working voltage across the barrier from equation 1 is 22 dc rmsac rms vvv ? ? 22 400240 ?? rms v v rms = 466 v rms this working voltage of 466 v rms is used together with the material group and pollution degree when looking up the creepage required by a system standard. to determine if the lifetime is adequate, obtain the time varying portion of the working voltage. obtain the ac rms voltage from equation 2. 22 dc rms rmsac vvv ?? 22 400466 ?? rmsac v v ac rms = 240 v rms in this case, ac rms voltage is simply the line voltage of 240 v rms. this calculation is more relevant when the waveform is not sinusoidal. the value of the ac waveform is compared to the limits for working voltage in table 8 for expected lifetime, less than a 60 hz sine wave, and it is well within the limit for a 20-year service life. note that the dc working voltage limit in table 8 is set by the creepage of the package as specified in iec 60664-1. this value may differ for specific system level standards.
data sheet adum4136 rev. 0 | page 15 of 16 typical application the typical application schematic in figure 29 shows a bipolar setup with an additional r blank resistor to increase charging current of the blanking capacitor for desaturation detection. the r blank resistor is optional. if unipolar operation is desired, remove the v ss2 supply, and tie v ss2 to gnd 2 . v i + 1 v i ? 2 v dd1 3 v ss1 4 gnd 2 16 v ss2 15 desat 14 v dd2 13 reset 5 v dd2 12 fault 6 v out 11 ready 7 v ss2 10 v ss1 8 v ss2 9 adum4136 c1 r blank c blank + v ce ? i c c2 c3 r gon r desat v rdesat +? v f ?+ r goff notes 1. grounds on primary and secondary side are isolated from each other. 13575-029 11 1 2 figure 29. typical application schematic
adum4136 data sheet rev. 0 | page 16 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b fig ure 30. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters (inches) ordering guide model 1 temperature range package description package option ADUM4136BRWZ ?40c to +125c 16-lead standard small outline package [soic_w] rw-16 ADUM4136BRWZ-rl ?40c to +125c 16-lead standard small outline package [soic_w], 13 tape and reel rw-16 eval-adum4136ebz evaluation board 1 z = rohs compliant part. ?2016 analog devices, inc. all rights reserved. tra demarks and registered trademarks are the property of their respective o wners. d13575-0-7/16(0)

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